1. Field of the Invention
This invention relates to clock and data recovery circuits and, more particularly, to techniques for clock and data recovery.
2. Description of the Related Art
High-speed data communication systems frequently rely on clock and data recovery (CDR) circuits within the receiver instead of transmitting a reference clock with the data. The CDR extracts a clock that is embedded in the incoming data stream. Once a clock is recovered, it is used to sample the incoming data stream to recover the individual bits. A variety of clock recovery circuits are well known, including phase-locked loops (both analog and digital) and delay lock loops. Regardless of the circuit used, a clock recovery circuit attempts to extract the frequency and phase of the clock from a data stream.
During propagation, data signals may experience distortion due to bandwidth limitations, dispersion, etc. in the communication channel. These effects cause a spreading of signal pulse energy from one symbol period to another. The resulting distortion is known as inter-symbol interference (ISI). Generally speaking, ISI becomes worse as the speed of communication increases. As a result, high-speed communication systems often incorporate circuitry to equalize the effects of ISI. One technique for reducing the effect of ISI is to use a Finite Impulse Response (FIR) filter in the transmitter to equalize the signal before transmitting it through the communication channel. Various parameters of the FIR determine the effect the FIR has on the signal. Various properties of the communications channel determine the appropriate settings of these FIR parameters. For example, signals passing through a communication channel may be affected by electrical properties as well as the temperature and humidity of the channel. Some of these properties may vary during operation, suggesting a need to vary FIR parameters during operation to maintain proper ISI equalization, particularly at high communication speeds.
In addition to the above considerations, proper functioning of the data receiver requires that the CDR recover a stable clock. To recover a stable clock, one type of CDR uses an algorithm known as the Muller-Mueller algorithm. Performance of the Muller-Mueller algorithm is improved if the received signal is equalized before being sampled. Theoretically, equalization may be improved by taking measurements of the pulse response of the communication channel in real time during high-speed communication and using them to set FIR parameters. However, capturing measurements of the channel's pulse response during high-speed operation is problematic. Theoretically, the height of the pulse response may be estimated at various points in time and these estimates used to determine settings of the FIR. For example, an estimate of the pulse height at the peak of the pulse may be referred to as the cursor height, an estimate of the pulse height one unit interval prior to the peak of the pulse may be referred to as the pre-cursor height, and an estimate of the pulse height one unit interval after the peak of the pulse may be referred to as the post-cursor height, where a unit interval is the time between successive symbols in the channel. A FIR may be constructed with three tap coefficients that correspond to the pre-cursor, cursor, and post-cursor heights. In most implementations of the Muller-Mueller algorithm, a locking position of the recovered clock phase occurs for a pre-cursor height of zero. Consequently, it is not possible to use a zero-forcing algorithm to adapt the pre-cursor tap coefficient. Unfortunately, using a pre-cursor tap coefficient value of zero may not produce optimum equalization or result in the cursor being at the peak of the pulse response. In view of the above considerations, systems and methods of efficiently adapting equalization values such as the FIR coefficients are desired.